Physics-driven Modeling and Simulation for Hybrid CMOS and Carbon Nanotubes 3D Integration for Energy.PHIDANIE

European Union

Status: submitted project
Contract Number:

The objectives of the proposed multidisciplinary research project are two fold: (1) to develop physics-driven models and simulation techniques, (2) for exploring energy
efficiency on hybrid 3D integration of CMOS and carbon nanotubes (CNT) nanoelectronics circuits. These circuits will combine a CMOS subsystem with several layers of carbon nanotubes as local to global interconnects. Such approach combines the advantages of CMOS technology, including its high flexibility, functionality and yield, with the extremely high density CNT interconnects. As a result, 3D hybrid of CMOS and CNTs can overcome limitations pertinent to other 3D integration techniques (such as copper through-silicon vias) and enable 3D circuits with unprecedented aggregate interconnect layer for power supply and communication bandwidth (up to 1018 bits per second per cm2). Such advantages represent a step forward into energy efficiency and addressing the most pressing need of modern nanoelectronics circuits.


The objectives of the PHIDANIE project are:
OBJ. 1. Benchmarking of carbon nanotubes for on- and off-chip interconnects.Here, we aim to experimentally grow CNT interconnects of different geometries and report on the fabrication and characterization. Workpackage 1 (WP1) and 3 (WP3) will be partially devoted to this objective, where the main research steps will be:
a. Fabrication and processing methods for mechanically robust CNTs.
b. Characterization of CNT interconnects and examination of their electrical and thermal
c. Characterization of junction bonding i.e. CNT-to-CNT and CNT-to-Cu metal contact resistance.
d. Provide experimental validation and scientific foundation for the proposed CNT interconnect
models in this project.
OBJ. 2. Modeling and simulation of CNT on- and off-chip interconnects.
Based on the measurements obtained from benchmarking, research efforts will be dedicated on
modeling and simulation of CNTs interconnects. Workpackage 1 (WP1) and 3 (WP3) are partially dedicated to this objective. The main research steps will be:
a. Simulation and modeling of CNT on-chip interconnect i.e. defective structure of CNTs, CNT-to-CNT junctions, and CNT-to-metal junctions.
b. Simulation and modeling of CNT TSVs i.e. defective structure of CNT TSVs and junctions.
c. Development of electrical and thermal models of CNT on- and off-chip interconnects that are usable at device-, circuit- and system-level simulations
OBJ. 3. Modeling and simulation of scaled CMOS devices with CNT interconnects
Here, we aim to model and simulate the impact of CNT local interconnects on the performance of CMOS transistors and standard cells, including SRAM cells. Apart from key figures of merit including, drive current, leakage and DIBL; we will study the impact of noise, variability and reliability. Such device-level simulation can support the extraction of early information on feasibility and device performance for the proposed 3D hybrid integration. The main research topics will be:
a. Development of 10nm CMOS technology template FDSOI and FinFET transistors.
b. Simulation study of statistical reliability and variability in the presence of CNT interconnects.
c. Extraction of transistor compact models and local interconnect RC components.
d. Development of limited set standard cell design and characterization to allow the study of high level CNT interconnects using STA and SSTA.
OBJ. 4. Design space exploration for energy efficiency
Leveraging on models for CNTs (on- and off-chip interconnects) with scaled CMOS device models from WP1, WP2 and WP3, we will focus on circuit- and system-level modeling and design flow for exploring energy efficiency. WP4 is fully devoted to this objective. The key research topics will be:
a. Circuit- and system-level modeling of 3D hybrid with scaled CMOS devices and CNTs.
b. Implementation of 3D hybrid circuit design flow.
c. 3D hybrid design space exploration for energy efficiency.
d. Investigate design techniques to improve power and thermal integrity by exploiting CNT TSVs.


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